Automatic Test Reordering for Electrical and Thermal Stress during Monitored Burn-in

As the conlplexity of VLSI circuits increases, the semiconductor manufacturers progress towards in-situ monitored burn-in to improve the quality and reliability of their products. A new method is proposed to control the switching current drawn by a. CMOS circuit during burn-in ancl test applications. This is basecl on reordering of the test vectoi:~ such that the circuit activity or electrical stress is modified as specified by the designer. or the quality control engiineer during monitored burn-in. Results on several ISCAS-89 benchmarks show that the current (or power dissipation) requirement of a circuit can be changed by more than a factor of 4 by reordering the input test vectors. We have developecl a CAD tool which can reorder tests for monitored burn-in to achieve average switching cilrre~it within 5% of the specified value. The technique can also be used to selectively produce higher switching activity in specified portions of the circuit to produce sharp temperature gradient inside the chip. Such temperature gradient can weed out defects such as crystal anomalies, junction imperfections etc, which might otherwise show up during the infant morta1,ity period.